System-on-chip
system on chip (SoC or SOC into a single functions – all on one chip. A typical application is in the area of ) is an idea of integrating all components of a computer or other electronic systemintegrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequencyembedded systems.
If it is not feasible to construct an SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. However, SoC is believed to be more cost effective since it increases the yield of the fabrication and also its packaging is less complicated compared to a SiP.
SOC structure
A typical SoC consists of:
- One or more microcontroller, microprocessor or DSP core(s).
- memory blocks including a selection of ROM, RAM, EEPROM and Flash.
- Timing sources including oscillators and phase-locked loops.
- Peripherals including counter-timers, real-time timers and power-on reset generators.
- External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI.
- Analog interfaces including ADCs and DACs.
- Voltage regulators and power management circuits.
These blocks are connected by either a proprietary or industry-standard bus such as the AMBA bus from ARM. DMA controllers route data directly between external interfaces and memory, by-passing the processor core and thereby increasing the data throughput of the SoC.
Design flow
An System on Chip consists of the hardware described above, but also of the software that controls the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for an SoC aims to develop this hardware and software in parallel.
Most SoCs are developed from pre-qualified blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using CAD tools; the software modules are integrated using a software development environment.
A key step in the SoC design flow is emulation: the hardware is mapped onto an emulation platform based on a FPGA that then mimics the behavior of the SoC, and the software modules are loaded into the memory of the emulation platform. Once programmed, the emulation platform enables both the hardware and the software of the SoC to be tested and debugged at close to its full operational speed.
After emulation the hardware of the SoC follows the place and route phase of the design of an integrated circuit before it is fabricated.
ASIC Verification: Chips are verified for their logical correctness before sending them to foundry. The process is called ASIC verification. Verilog and VHDL are the Hardware Descriptive languages used for verification. With growing complexity of Chips HVLs like SystemVerilog, SystemC, e, Vera are used. The bugs found in the verification stage are reported to the designer. Traditionally 70% of time and energy in Chip design life cycle are spent on Verification.
Fabrication
SoCs can be fabricated by several technologies, including:
- Full-custom
- Standard cell
- FPGA
SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well.
However, like most VLSI designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields and higher NRE costs.